Storage System and Method for Adaptive Scheduling of Background Operations

ABSTRACT

A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. patent application Ser. No. 15/465,367, filed Mar. 21, 2017, which is hereby incorporated by reference.

BACKGROUND

A storage system can have a memory that is organized into blocks. Over time, data written in a block can be invalidated (e.g., because of host data deletion and/or data transfers internal to the storage system). Garbage collection is a process that collects the valid parts of used memory blocks (ignoring the invalidated parts) and moves them to a new block. When a block is fully invalidated, it is returned to the free block pool. Garbage collection can be controlled by keeping a “valid counter” for each block to track the number of valid flash management units in the block and/or by a program/erase cycle counter to monitor the block's endurance. A garbage collection algorithm can choose which block should be “collected” next by checking which block has the lowest “valid counter,” the highest program/erase cycle counter, and/or a program/erase cycle counter that is below average.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a non-volatile storage system of an embodiment.

FIG. 1B is a block diagram illustrating a storage module of an embodiment.

FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment.

FIG. 2A is a block diagram illustrating components of the controller of the non-volatile storage system illustrated in FIG. 1A according to an embodiment.

FIG. 2B is a block diagram illustrating components of the non-volatile memory storage system illustrated in FIG. 1A according to an embodiment.

FIG. 3 is a flow chart of a method for predictive block allocation for efficient garbage collection of an embodiment.

FIG. 4 is a flow chart of a method for storing patterns in a memory of an embodiment.

FIG. 5 is a flow chart of a method for predictive block allocation for efficient garbage collection of an embodiment in which pattern matching is used.

FIG. 6 is a graph showing a latency margin for a host operation of an embodiment.

FIG. 7 is a flow chart of a method of an embodiment for utilizing high-power latency to perform background operations.

FIG. 8 is a flow chart of a method for storing patterns in a memory of an embodiment.

FIG. 9 is a flow chart of a method of an embodiment for adaptive scheduling of background operations by comparing commands and logical block addresses against stored command and logical block address patterns.

DETAILED DESCRIPTION

By way of introduction, the below embodiments relate to a storage system and method for predictive block allocation for efficient garbage collection. In one embodiment, a method for block allocation is provided. The method comprises determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

In some embodiments, the determining is performed by comparing a plurality of write commands to patterns stored in the storage system, wherein the first block allocation method is associated with one of the patterns, and wherein the second block allocation method is associated with another one of the patterns.

In some embodiments, the determining is performed using machine learning. In some embodiments, the machine learning uses supervised learning, whereas, in other embodiments, the machine learning uses unsupervised learning.

In some embodiments, the determining is performed by calculating a ratio of user single address updates versus drive rewrites.

In some embodiments, the determining is performed by receiving an indication from a host as to whether the memory is being used in the first usage scenario or in the second usage scenario.

In some embodiments, the method further comprises altering a time of garbage collection.

In some embodiments, the time of garbage collection is altered by adjusting at least one threshold parameter for initiating garbage collection.

In some embodiments, the time of garbage collection is altered by altering a ratio of triggering garbage collection operations versus host write.

In some embodiments, the time of garbage collection is altered by altering a ratio of dynamic versus static garbage collection operations.

In some embodiments, data stored in the first usage scenario is updated less frequently than data stored in the second usage scenario.

In some embodiments, the memory comprises a three-dimensional memory.

In some embodiments, the method is performed in the storage system.

In another embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands; compare the plurality of write commands to patterns stored in the storage system; for each pattern, generate a score that represents a matching level of the plurality of write commands to that pattern; determine which score exceeds a threshold; and choose a block allocation scheme associated with the pattern whose score exceeds the threshold.

In some embodiments, a block allocation scheme associated with a first pattern allocates blocks that are closer to needing garbage collection than a block allocation scheme associated with a second pattern.

In some embodiments, the controller is further configured to adjust at least one threshold parameter for initiating garbage collection.

In some embodiments, the memory comprises a three-dimensional memory.

In some embodiments, the storage system is embedded in a host.

In some embodiments, the storage system is removably connected to a host.

In another embodiment, a storage system is provided comprising a memory; means for determining how the memory is being used; and means for choosing a block allocation method based on how the memory is being used, wherein a first block allocation method is chosen in response to determining that the memory is being used in a first usage scenario, and wherein a second block allocation method is chosen in response to determining that the memory is being used in a second usage scenario, further wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

In some embodiments, the means for determining and the means for choosing comprise a controller.

In some embodiments, the memory comprises a three-dimensional memory.

In another embodiment, a method for adaptive scheduling of a background operation is provided that is performed in a storage system in communication with a host, wherein the storage system is configured to operate in a high power mode and a low power mode and comprises a memory. The method comprises completing a host operation in the memory, wherein the storage system is in the high power mode when performing the host operation and remains in the high power mode for a period of time following the completion of the host operation, after which the storage system enters the low-power mode; estimating whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation; and in response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, performing the background operation in the memory.

In some embodiments, the storage system estimates whether there will be enough time by comparing write commands received from the host to patterns stored in the storage system, wherein a matching pattern provides a prediction of how long it will be before another host operation will be received.

In some embodiments, the method further comprises generating a score for each pattern stored in the storage system that represents a matching level to the received write commands; comparing the scores against a threshold; and selecting a pattern that satisfies the threshold.

In some embodiments, the storage system uses machine learning to perform the estimating.

In some embodiments, the memory comprises a three-dimensional memory.

In some embodiments, the storage system is embedded in the host.

In some embodiments, the storage system is removably connected to the host.

In another embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. The controller is configured to enter a high power mode to perform a foreground operation; remain in the high power mode during a latency margin after the foreground operation is performed; and predict whether there is enough time remaining in the latency margin to perform a background operation before another foreground operation needs to be performed.

In some embodiments, the controller is configured to perform the predicting by comparing a pattern of write commands received from a host to a stored plurality of patterns of write commands.

In some embodiments, the plurality of patterns of write commands are stored in the storage system when the storage system is off-line with respect to the host.

In some embodiments, the controller is further configured to score each of the stored plurality of patterns of write commands against the pattern of write commands received from the host to determine a match.

In some embodiments, the controller is configured to use machine learning to perform the predicting.

In some embodiments, the memory comprises a three-dimensional memory.

In some embodiments, the storage system is embedded in a host.

In some embodiments, the storage system is removably connected to a host.

In another embodiment, a storage system is provided comprising a memory; means for determining whether the storage system should perform a background operation while the storage system is still in a high power mode after performing a host command, wherein the storage system is in the high power mode for a predetermined period of time prior to entering a low power mode; and means for performing the background operation in response to determining that the storage system should perform the background operation.

In some embodiments, the means for determining uses pattern matching.

In some embodiments, the means for determining uses machine learning.

In some embodiments, the means for determining predicts whether the host will send a command that will interrupt performance of the background operation.

In some embodiments, the memory comprises a three-dimensional memory.

Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.

Turning now to the drawings, storage systems suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A -1C. FIG. 1A is a block diagram illustrating a non-volatile storage system 100 according to an embodiment of the subject matter described herein. Referring to FIG. 1A, non-volatile storage system 100 includes a controller 102 and non-volatile memory that may be made up of one or more non-volatile memory die 104. As used herein, the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate. Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die 104.

The controller 102 (which may be a flash memory controller) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The controller 102 can be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.

As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionality in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory to ensure the memory is operating properly, map out bad flash memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide the physical address.) The flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused).

Non-volatile memory die 104 may include any suitable non-volatile storage medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a two-dimensional or three-dimensional fashion.

The interface between controller 102 and non-volatile memory die 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, storage system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, storage system 100 may be part of an embedded storage system.

Although, in the example illustrated in FIG. 1A, non-volatile storage system 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104, the subject matter described herein is not limited to having a single memory channel. For example, in some NAND storage system architectures (such as the ones shown in FIGS. 1B and 1C), 2, 4, 8 or more NAND channels may exist between the controller and the NAND memory device, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.

FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100. As such, storage module 200 may include a storage controller 202 that interfaces with a host and with storage system 204, which includes a plurality of non-volatile storage systems 100. The interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface, such as a serial advanced technology attachment (SATA) or peripheral component interface express (PCIe) interface. Storage module 200, in one embodiment, may be a solid state drive (SSD), such as found in portable computing devices, such as laptop computers, and tablet computers.

FIG. 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a respective storage system 204. Host systems 252 may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be an NVMe or fiber channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C may be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.

FIG. 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104, and various other modules that perform functions which will now be described in detail. A module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. Modules of the controller 102 may include a block allocation module 111, which is discussed in more detail below, and can be implemented in hardware or software/firmware. Also, as will become clear from the below, the controller 102, along with a hardware and/or software configuration to perform the algorithms discussed herein and shown in the drawings, can provide means for predicting usage behavior of the memory and means for allocating a block based on the predicted usage behavior.

Referring again to modules of the controller 102, a buffer manager/bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102. A read only memory (ROM) 118 stores system boot code. Although illustrated in FIG. 2A as located separately from the controller 102, in other embodiments one or both of the RAM 116 and ROM 118 may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller 102 and outside the controller.

Front end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface 120 can depend on the type of memory being used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 typically facilitates transfer for data, control signals, and timing signals.

Back end module 110 includes an error correction controller (ECC) engine 124 that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory device 104. In some cases, the RAID module 128 may be a part of the ECC engine 124. A memory interface 130 provides the command sequences to non-volatile memory die 104 and receives status information from non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of back end module 110.

The storage system 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller 102. In alternative embodiments, one or more of the physical layer interface 122, RAID module 128, media management layer 138 and buffer management/bus controller 114 are optional components that are not necessary in the controller 102.

FIG. 2B is a block diagram illustrating components of non-volatile memory die 104 in more detail. Non-volatile memory die 104 includes peripheral circuitry 141 and non-volatile memory array 142. Non-volatile memory array 142 includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration. Peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102. Non-volatile memory die 104 further includes a data cache 156 that caches data.

As mentioned above, a storage system can have a memory that is organized into blocks. (As used herein, a block is a set of memory cells.) Over time, data written in a block can be invalidated (e.g., because of host data deletion and/or data transfers internal to the storage system). Garbage collection is a process that collects the valid parts of used memory blocks (ignoring the invalidated parts) and moves them to a new block. When a block is fully invalidated, it is returned to the free block pool. Garbage collection can be controlled by keeping a “valid counter” for each block to track the number of valid flash management units in the block and/or by a program/erase cycle counter to monitor the block's endurance. A garbage collection algorithm can choose which block should be “collected” next by checking which block has the lowest “valid counter,” the highest program/erase cycle counter, and/or a program/erase cycle counter that is below average.

Garbage collection may hinder host performance as it uses the interface from the storage system's controller to the memory and also uses space in both the storage system's controller and memory. Efficient garbage collection, both in terms of memory and performance, is very useful. The following embodiments provide a method for predicting usage behavior and choosing a block allocation method that will effectively alter garbage collection. That is, these embodiments can use the predicted behavior of a user or host in the process of choosing the next block to allocate and/or in the process of choosing the garbage collection schedule. By using adaptive block allocation in the process of garbage collection, based on the usage scenario of current device, these embodiments can be used to provide a more-efficient approach than prior designs.

Turning now to the drawings, FIG. 3 is a flow chart 300 of a method of an embodiment for predictive block allocation for efficient garbage collection. As shown in FIG. 3, in this embodiment, the storage system 100 (e.g., the controller 102 or the block allocation module 111) determines whether the memory is being used in a first usage scenario or a second usage scenario (act 310). In response to determining that the memory 104 is being used in the first usage scenario, the storage system 100 uses a first block allocation method (act 320). Conversely, in response to determining that the memory 104 is being used in the second usage scenario, the storage system 100 uses a second block allocation method (act 330). In one embodiment, data stored in the first usage scenario is updated less frequently than data stored in the second usage scenario, and the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method. In one embodiment, one block can be closer to needing garbage collection than another block if that block has a parameter (e.g., a value of a valid flash management unit (FMU) counter and/or a program/erase cycle counter) that is closer to the threshold for initiating garbage collection.

For example, there can be a clear distinction between block allocation for storage systems/memories that are used for streaming videos (extreme use case: where the entire memory 104 (e.g., flash drive) is written and then rewritten immediately, time after time) and storage systems/memories that are used for updating something online (use case: where the same logical block address (LBA) is written over and over again, such as when written a log file, doing maintenance, or performing a single address update). In the first usage scenario (drive rewrite), block allocation can be done in a more “conservative” fashion since all the data is valid, and there is no system gain of releasing blocks by garbage collection operations. However, in the second usage scenario, block allocation can be done in a more “aggressive” fashion since only few flash management units (FMUs) are valid, and there is high incentive to revive blocks fast by garbage collection operations.

So, data written in the first usage scenario (e.g., “cold storage”) can be allocated to blocks that are close to their garbage-collection-initiation threshold (e.g., blocks with a high program-erase cycle (PEC) counter). Even though the blocks are close their garbage-collection-initiation threshold, because the data will not be re-written (or have a limited number of re-writes), there is a low chance that the blocks will need garbage collection in the near term. Plus, these types of blocks would not be ideal for situations where there are multiple re-writes (the second usage scenario) because frequent re-writes to blocks that are close to their garbage-collection-initiation threshold will trigger garbage collection, which may not be preferred, as discussed above.

In contrast, data written in the second usage scenario (e.g., “many rewrites”) can be allocated to blocks that are farther away from their garbage-collection-initiation threshold (e.g., blocks with a low program-erase cycle (PEC) counter or a block that has been freshly garbage collected or has garbage collected ahead of schedule). Such blocks are better suited for data that will be re-written than blocks that are closer to their garbage-collection-initiation threshold (e.g., blocks with a high program-erase cycle (PEC) counter), as such blocks are withstand more re-writes before reaching the garbage-collection-initiation threshold.

As can be seen from these examples, choosing a block allocation method based on predicted usage behavior effectively alters when garbage collection takes place, since whether an allocated block is relatively closer to or farther away from needing garbage collection affects when garbage collection on that block occurs. As noted above, garbage collection may hinder host performance as it uses the interface from the storage system's controller 102 to the memory 104 and also uses space in both the storage system's controller 102, memory 104, and/or RAM 116. Using block allocation based on usage behavior can provide efficient garbage collection, both in terms of memory and performance. These embodiments can also reduce the memory over-provisioning needed for efficient garbage collection operations, as the overall number of allocated blocks throughout the storage system's lifetime can be lower for the same data input. These embodiments can also increase endurance and performance when the memory 104 is full.

While only two usage scenarios were discussed in the above example, it should be noted that there can be many usage scenarios in between these. In one embodiment, the storage system 100 is configured to dynamically set the block allocation scheme between “conservative” and “aggressive” based on the user's behavior or usage scenario.

There are many alternatives that can be used with these embodiments. For example, the determination of whether the memory 104 is being used in a first usage scenario or a second usage scenario (or any number of usage scenarios) can be done in any suitable way. For example, in one embodiment, the determining is performed by receiving an indication from a host as to whether the memory 104 is being used in the first usage scenario or in the second usage scenario. In another embodiment, the determining is performed by the storage system 100 (e.g., with the controller 102 being programed with an algorithm that decides whether the storage system 100 / memory 104 is being used in a first usage scenario, a second usage scenario, etc., or neither/none of them. For example, in one embodiment, the controller 102 compares a plurality of write commands to patterns stored in the storage system 100. This example will be discussed in more detail in conjunction with FIGS. 4 and 5.

As shown in FIG. 4, the write patterns corresponding to various write scenarios can be stored in memory 104 (or in another storage location (e.g., ROM 118) in the storage system 100) when the storage system 100 is offline (e.g., during production, but, in one embodiment, the stored pattern can be updated during the life of the storage module 100) (act 410). For example, a number (N) of patterns can be stored that embody the patterns that optimized block allocation may be related to (e.g., a first block allocation method can be associated with one of the patterns, and a second block allocation method can be associated with another one of the patterns). A successful classification to a pattern can result in block allocation optimization for that pattern. These patterns can include, for example, logical block addresses (LBAs) or LBA ranges that a user is expected to write for a given usage scenario. The LBA write history of the user/host can be recorded and can be matched against each of the stored patterns.

FIG. 5 is a flow chart 500 of a method of one embodiment that matches write addresses from write commands received by the storage system 100 against write address patterns stored in the storage system 100. In this embodiment, the acts in this flow chart 500 are performed when the storage system 100 is online. As shown in FIG. 5, in this embodiment, the storage system 100 (e.g., the controller 102 or the block allocation module 111) continuously tests write address patterns from a plurality of write commands received by the storage system 100 against patterns stored in the storage system 100 (act 510). The storage system 100 then generates a score for each stored pattern that represents a matching level of the current write pattern to the stored pattern (act 520). So, for each of the stored patterns, a score that represents the pattern's matching to the user write history is be generated. The storage system 100 then checks the matching score against a threshold (act 530). If there is a low match, the process begins again at act 510. However, if there is a high match, the storage system 100 changes the block allocation scheme according to the detected write pattern (act 540). Accordingly, if one of the scores passes a certain threshold, then a successful match is declared. So, for example, if one of the patterns depicts constantly writing the same small range of LBAs, and a user is constantly writing 1 LBA (or a range of <100 LBAs), this pattern can be identified, and the indication can be passed to the block allocation unit, which will then act according to the “single address rewrite” usage scenario discussed above.

It should be noted that the above algorithm was just an example, and other algorithms and methods can be used. Further, many other alternatives can be used with these embodiments. For example, in addition to or as an alternative to the matching process discussed above, a “soft” measure, which can represent the pattern's matching to the user history, can be generated and used in the block allocation process, for example, by predicting of usage behavior using machine learning. In this alternative, a machine learning algorithm can be used for learning the user's access patterns and, accordingly, make the decision on the garbage collection policy (e.g., aggressive versus conservative schemes). The pattern recognition may be performed using a support vector machine (SVM) classification, a neural network, or other clustering methods, such as K-Means and/or the principal component analysis (PCA) method. Supervised (pre-calibrated) or unsupervised learning algorithms can be used (i.e., the training/calibration of the algorithm can be done with or without a labeled dataset that includes ground truth labels of relevant training examples (or even without pre-training/calibration of the model, where classifying is done directly (adaptive learning) during the life time of the device). As yet another example, the storage system 100 can predict usage behavior by calculating a ratio of the single address updates versus drive rewrites and, accordingly, adapt the ratio of triggering garbage collection operations versus host writes and/or the ratio of dynamic versus static garbage collection operations. Further, instead of the storage system 100 doing the predicting, the host can do the predicating and send an indication of the results to the storage system 100.

Further, in addition to or instead of allocating blocks based on usage behavior, the storage system 100 can alter the time of garbage collection initialization by adjusting at least one threshold parameter for initiating garbage collection in a block of memory 104. Examples of threshold parameters include, but are not limited to, a number of valid units in the block and a number of program/erase cycles performed in the block. As another example, the time of garbage collection initialization can be altered by performing garbage collection in a block ahead of schedule (e.g., in response to predicting that data to be stored in the block will have frequent updates).

In some of the above embodiments, the scheme of block allocation for garbage collection was determined according to an estimation of the user's inclination to frequently overwrite data. In another embodiment, a similar estimation mechanism can be used to provide a solution to a different problem; namely, using an estimation mechanism for adaptive scheduling of background operations during the time in which a user power mode requires minimum excess power. For example, in one embodiment, a storage system can use machine learning to determine whether the host/user will remain in high power mode for the duration of any of the background operations currently queued. Other embodiments are presented below.

As used herein, a background operation is in contrast to a foreground (or host/user) operation, which is an operation that is preferably performed to completion without being interrupted and typically has a predetermined completion time. A foreground command is typically issued by the host controller and sent to the storage system 100 for execution. Examples of a foreground command include, but are not limited to, a read command, a write command, and an erase command.

A background command can be performed whenever possible when no host foreground commands are currently being executed and after a period of idle time. Examples of background operations include, but are not limited to, garbage collection, read threshold calibration, time tag split or union, relocation of data to multi-level cells (such as a triple-level cell (TLC) or a quad-level cell (QLC)), data scrambling, column replacement, handling write aborts and/or program failures (via safe zones), read scrubbing, wear leveling, bad block and/or spare block management, error detection code (EDC) functionality, status functionality, encryption functionality, error recovery, and address mapping (e.g., mapping of logical to physical blocks). In some embodiments, a background operation can be preempted/interrupted by a foreground command and continued at a later time. Unlike foreground commands which can have a predetermined completion time, some background commands can have an uncertain completion time, depending on how much they are interrupted by foreground commands.

The power that is drawn from a power source of the storage system for a background management operation can take a significant portion of the storage system's power budget. Accordingly, the timing of these background operations is important for good power management. Good power management can be especially important with devices that contain embedded memory and in client/user storage devices. The power supply can play an important role in these devices, and, as these devices become smaller, their power supplies also become smaller, and the power limitations become stricter.

The storage system 100 in this embodiment is configured to work in a high-power mode and a low-power mode. As used herein, a high-power mode refers to a mode used by the storage system 100 when the storage system 100 is used to store or read data from the memory 104. In contrast, a low-power mode refers to a mode used by the storage system 100 when the storage system 100 is not used to store or read data from the memory 104. Low-power mode uses less power from the power supply of the storage system 100 than high-power mode. For example, in low-power mode, slower performance can be used to draw less power and/or certain hardware components (e.g. volatile memory) can be powered-off. It should be noted that “high” and “low” in this context are meant in a relative context (i.e., the storage system 100 uses more power in high-power mode than in low-power mode); they do not necessarily infer a particular power level.

As noted above, a host operation (e.g., a read, write, or erase operation) can have a predetermined completion time, and the storage system 100 is in the high-power mode to execute the operation. After the host operation is completed in the memory 104 (e.g., data is read from or written to the memory), the storage system 100 can switch to the low-power mode. In some implementations, the host can provide the storage system 100 with a power policy that specifies a certain maximum latency for staying in high-power mode after the storage system 100 completes the host operation. This is illustrated in FIG. 6, which shows that the storage system 100 is in high-power mode for a period of time after the end of the host operation. After that period of time has elapsed (i.e., at the end of the declared margin), the storage system 100 returns to the low-power mode. This margin of latency is provided over the typical latency to complete the host operation in the memory 104 to allow for any problems that might occur in executing the host operation. For example, while it might occur infrequently, it is possible for a host operation to encounter cascading errors that require time for recovery steps. By providing the margin of latency, these recovery steps can be performed while the storage system 100 is still in high-power mode. If this margin of latency were not provided, the storage system 100 would transition to low-power mode and then transition back to high-power mode, and the transitional energy cost of doing so might be very high and put strain on the power budget of the storage system.

The following embodiments are directed to performing one or more background operations in the memory 104 of the storage system 100 during this margin of latency to take advantage of the fact that the storage system 100 is still in the high-power mode (i.e., to utilize the latency margin after completing a host operation to schedule and execute a background operation, as the storage system 100 would still be in high power mode). While background operations can be performed at a later time when the host is idle, that would likely require the storage system 100 to transition from the low-power mode to the high-power mode, and, as noted above, the transitional energy for transitioning from the low-power mode to the high-power mode can be high.

However, it is possible that the host may issue another command to the storage system 100 during the latency window, and the storage system 100 would need to execute that command instead of the background operation. That means that if the storage system 100 were to start a background operation in the latency window and then receive a host command before the background operation is completed, the new host command may interrupt and preempt the background operation. This interruption/preemption can result in more power consumption than if the storage system 100 just waited to perform the background operation at a later time.

To address this issue, the following embodiments can be used by the storage system 100 to estimate whether or not there is enough time in the latency window for the storage system 100 to perform the background operation. This estimation can be based on a prediction of the likelihood that the host/user will issue another command in that window, which can be based on prior host/user behavior. FIG. 7 is a flow chart 700 of one example method that can be used.

As shown in FIG. 7, after the storage system 100 finishes performing the host command (act 710), the storage system 100 determines if there is any time remaining in the latency window (act 720). As noted above, the host can provide the storage system 100 with a power policy that specifies the period of time of the latency window. If there is a problem with executing the host operation, some or all of the time in the latency window may be used to deal with the problem.

If there is time remaining in the latency window, the storage system 100 then estimates whether there is enough time left in the latency window to perform one or more background operations, which may be queued up in the storage system 100 (e.g., according to their importance and/or length) (act 730). As will be discussed in more detail below, this estimate can be based on a prediction of the likelihood of the host sending another command in the latency window based on prior behavior by the host. If the storage system 100 estimates that there will be enough time, the storage system 100 executes a background operation (act 740). It should be noted that the estimate is just an estimate, which may be right or wrong. If the estimate is right, the storage system 100 saves power by taking advantage of the existing high-power mode to execute the background operation (instead of spending power to later transition from the low-power mode to the high-power mode to execute the background operation). Provided that the estimate is right, these embodiments provide several advantages, such as, but not limited to, overall latency reduction, better performance (through better-timed background operations and their positive impact on performance), and reduced peak-power consumption (as the power consumption of background operations will be better timed). This improves power consumption and overall read latency, which includes background operations. However, if the estimate is wrong and a host command is received in the latency window while the background operation is being executed, the storage system 100 may spend more power than it would have.

As mentioned above, any suitable technique can be used to estimate if there will be enough time for the storage system 100 to execute the background operation in the latency window. For example, the techniques described above for estimating a user's inclination to frequently overwrite data can be adapted for these embodiments to estimate remaining time in high power mode. This will now be discussed in conjunction with FIGS. 8 and 9.

As shown in FIG. 8, N number of patterns corresponding to various host operation scenarios can be stored in memory 104 (or in another storage location (e.g., ROM 118) in the storage system 100) when the storage system 100 is offline (e.g., during production, but, in one embodiment, the stored pattern can be updated during the life of the storage module 100). These patterns can embody the patterns that power mode prediction may be related to (i.e., any successful classification to any of these patterns will result in power mode prediction). For example, a number of patterns of host operations (e.g., write and/or read), along with their associated logical block addresses (LBAs) or LBA ranges, can be stored, along with their matching power scores, in the storage system 100 (act 810). For each pattern, the matching power score can indicate if and when another host command was received in the latency window following that pattern. The algorithm can classify several set classes of power usage or do a regression, where it predicts a power figure that is considered as the power that will be drawn from the power supply by the host. These patterns can consist of the commands the user passed and the LBAs (or LBA ranges) that the user is expected to be writing.

The LBA write history and the commands passed by the user can be recorded and matched against each of the stored patterns. In general, for each of the stored patterns, a score that represents the pattern's matching to the user write history can be generated. Eventually, the results can be aggregated, and an evaluated time at high power mode can be produced. A “soft” measure representing the pattern's matching to the user history can also be generated and used in the high power time evaluation. For example, one of the patterns can embody writing with high frequency over the same small range of LBAs. In such case, the storage system 100 can conclude that the user will remain in high power mode during the mentioned “excess margin” and, thus, that a background operation can be performed during that time.

FIG. 9 depicts the process of LBA matching against the stored patterns, in which the storage system 100 uses the stored patterns to determine whether or not to execute a background operation in the latency window. As shown in shown in FIG. 9, when the storage system 100 is in use with a host (“online”), the storage system 100 receives a new command from the host and initiates a pattern evaluation based on that command and/or previous commands received by the storage system 100 (act 910). To do this, the storage system 100 can generate a score for each stored pattern that represents a matching level of the current write pattern to the stored pattern (act 920). The storage system 100 can then check the matching score against one or more thresholds (act 930). If the storage system 100 determines that pattern matching suggests that it is likely that there will not be enough time to execute the background operation (“Short time@High power mode evaluated”), the storage system 100 will not perform the background operation. However, if the storage system 100 determines that pattern matching suggests that it is likely that there will be enough time to execute the background operation (“Long time@High power mode evaluated”), the storage system 100 will perform the selected background operation (act 940).

It should be noted that the above algorithm was just an example, and other algorithms and methods can be used. For example, in addition to or as an alternative to the matching process discussed above, which can be performed using simple computational logic, a “soft” measure, which can represent the pattern's matching to the user history, can be generated and used, for example, by predicting of usage behavior using machine learning. In this alternative, a machine learning algorithm can be used for learning the user's access patterns and, accordingly, make the decision as to whether or not to perform the background operation in the latency window. The pattern recognition may be performed using a support vector machine (SVM) classification, a neural network, a recurring neural network, or other clustering methods, such as K-Means and/or the principal component analysis (PCA) method. Supervised (pre-calibrated) or unsupervised learning algorithms can be used (i.e., the training/calibration of the algorithm can be done with or without a labeled dataset that includes ground truth labels of relevant training examples (or even without pre-training/calibration of the model, where classifying is done directly (adaptive learning) during the life time of the device). Further, instead of the storage system 100 doing the predicting, the host can do the predicating and send an indication of the results to the storage system 100.

There are many alternatives that can be used with these embodiments. For example, in one alternate embodiment, the results of the high-power-mode estimation using one of the algorithms discussed above may be used to estimate whether the high power mode may resume without the context of the currently-completed host operation. For example, an integrated memory device may estimate whether the device is connected to an external power supply. In such case, there may be less restriction on the power that the background operations require.

Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured.

The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.

In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.

Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art.

It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with one another. 

What is claimed is:
 1. A method for adaptive scheduling of a background operation, the method comprising: performing the following in a storage system in communication with a host, wherein the storage system is configured to operate in a high power mode and a low power mode and comprises a memory: completing a host operation in the memory, wherein the storage system is in the high power mode when performing the host operation and remains in the high power mode for a period of time following the completion of the host operation, after which the storage system enters the low-power mode; estimating whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation; and in response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, performing the background operation in the memory.
 2. The method of claim 1, wherein the storage system estimates whether there will be enough time by comparing write commands received from the host to patterns stored in the storage system, wherein a matching pattern provides a prediction of how long it will be before another host operation will be received.
 3. The method of claim 2 further comprising: generating a score for each pattern stored in the storage system that represents a matching level to the received write commands; comparing the scores against a threshold; and selecting a pattern that satisfies the threshold.
 4. The method of claim 1, wherein the storage system uses machine learning to perform the estimating.
 5. The method of claim 1, wherein the memory comprises a three-dimensional memory.
 6. The method of claim 1, wherein the storage system is embedded in the host.
 7. The method of claim 1, wherein the storage system is removably connected to the host.
 8. A storage system comprising: a memory; and a controller configured to: enter a high power mode to perform a foreground operation in the memory; remain in the high power mode during a latency margin after the foreground operation is performed; and predict whether there is enough time remaining in the latency margin to perform a background operation before another foreground operation needs to be performed.
 9. The storage system of claim 8, wherein the controller is configured to perform the predicting by comparing a pattern of write commands received from a host to a stored plurality of patterns of write commands.
 10. The storage system of claim 9, the plurality of patterns of write commands are stored in the storage system when the storage system is off-line with respect to the host.
 11. The storage system of claim 9, wherein the controller is further configured to score each of the stored plurality of patterns of write commands against the pattern of write commands received from the host to determine a match.
 12. The storage system of claim 8, wherein the controller is configured to use machine learning to perform the predicting.
 13. The storage system of claim 8, wherein the memory comprises a three-dimensional memory.
 14. The storage system of claim 8, wherein the storage system is embedded in a host.
 15. The storage system of claim 8, wherein the storage system is removably connected to a host.
 16. A storage system comprising: a memory; means for determining whether the storage system should perform a background operation in the memory while the storage system is still in a high power mode after performing a host command, wherein the storage system is in the high power mode for a predetermined period of time prior to entering a low power mode; and means for performing the background operation in response to determining that the storage system should perform the background operation.
 17. The storage system of claim 16, wherein the means for determining uses pattern matching.
 18. The storage system of claim 16, wherein the means for determining uses machine learning.
 19. The storage system of claim 16, wherein the means for determining predicts whether the host will send a command that will interrupt performance of the background operation.
 20. The storage system of claim 16, wherein the memory comprises a three-dimensional memory. 